1. Field of the Invention
Embodiments of the present invention relate generally to integrated timing generators and more specifically to a generic flexible timer design.
2. Description of the Related Art
Integrated circuits frequently employ a timing pulse generator, or “timer,” to produce a set of related pulse signals that may be used to coordinate and control activity within the integrated circuit. A timer may have a plurality of clock outputs, where each clock output activates a specific portion of a client circuit within the overall integrated circuit that is being controlled. The timing relationship between the clock outputs is generally important to the proper function of the client circuits.
One particularly challenging type of timer generates multiple pulses within the time span of a single system clock cycle. The pulses are generated in response to an activation event, such as a control signal pulse or clock edge arriving on one or more designated timer input pins. The activation event triggers a sequence of events within the timer that produces the required output pulses. For example, an embedded static random access memory (SRAM) may receive a reference clock signal, as well as read and write enable signals. From an external viewpoint, the SRAM synchronously reads from a specified address or writes to a specified address, according to the reference clock signal and enable signals. Internally, however, the SRAM is generating a carefully staged sequence of timing pulses to activate pre-charge circuits, row and column drivers, sense amplifier circuits, and the like, within the time period of a single synchronous clock cycle. The detailed delay and phase specification for each of the timing pulses is determined based on predictive timing models of the circuits within the SRAM. The SRAM timer circuit is typically designed to meet the specific timing needs of the various client circuits internal to the SRAM.
The design effort associated with custom timer circuits is typically very costly and error prone. Furthermore, the predictive timing models of the client circuits are sometimes wrong or incomplete, causing a malfunction of the overall integrated circuit. The most common solution to such a malfunction is an expensive re-design and re-fabrication of the integrated circuit. This type of solution is increasingly expensive as mask costs continue to increase with each successive process node.
As the foregoing illustrates, what is needed in the art is a technique for designing custom timer circuits that can accommodate various modeling inaccuracies, while minimizing overall design effort and cost.